The present invention relates to a semiconductor device having a semiconductor substrate having a trench such as a trench capacitor formed on its surface and a manufacturing method thereof.
In recent years, Large Scale Integrated Circuits (LSIs) are widely used in the important parts of computers and communications equipment. Due to this, the performance of the overall system is closely related to the performance of an LSI itself. The improvement in the performance of the single LSI can be realized by improving integration, that is, making elements smaller.
Various problems, however, arise as elements are smaller. In case of a capacitor of a DRAM memory cell, for example, if the area of the capacitor is smaller, its capacity tends to decrease. As a result, software-related errors occur such as the content of memory is erroneously read or the storage content is destroyed by the a line.
As one of the capacitors effective for solving these problems, there is known a trench capacitor. The trench capacitor is intended to ensure necessary capacity by making use of the sides of a trench for the capacitor area.
The trench capacitor has been conventionally formed as follows.
Using photolithography and Reactive Ion Etching (to be referred to as RIE hereinafter), a trench is formed on a silicon substrate. After an arsenic doped glass film is deposited thereon, the arsenic within the arsenic doped glass film is diffused into the surface of the trench by solid phase diffusion and an impurity diffused layer of high impurity concentration which serves as a capacitor electrode (or plate electrode) is formed on the surface of the trench.
Lastly, after forming a capacitor insulating film on the surface of the trench, an arsenic doped amorphous silicon film which serves as a storage node is deposited, whereby the trench capacitor is completed.
The conventional formation method as stated above, however, has the following problems.
If using the RIE, a tapered trench is formed and the embedding shape of the storage node (which is the arsenic doped amorphous silicon film) tends to deteriorate. The deterioration in the embedding shape becomes more obvious if the diameter of the, trench is smaller. This makes it difficult to provide smaller elements.
In addition, as a result of the RIE during the trench formation, the surface of the trench becomes uneven and the electric field concentrates on the uneven portions, thereby disadvantageously decreasing the withstand voltage of the insulating film of the capacitor.
To solve the latter problem, it is proposed the surface of the trench is smoothed by means of Chemical Dry Etching (to be referred to as CDE hereinafter). If a collar oxide film is formed on the upper wall of the trench, the collar oxide film needs to be formed thick by a degree corresponding to that etched by the CDE due to the fact that large etching selectivity between the collar oxide film and the silicon substrate is not expected.
It is however difficult to form a thicker collar oxide film on the upper wall of the trench whose diameter has become narrower as the sizes of the elements including the trench have become smaller. For that reason, the above-stated CDE is not suitable for and inapplicable to the smaller-sized elements.
Furthermore, if an exposure mask of a rectangular pattern is used as an exposure make for trench formation to realize high density elements, then a trench having angular portions with a small radius of curvature is formed and the electric field concentrates on that angular portions with small radius of curvature. As a result, the withstand voltage of the capacitor insulating film disadvantageously deteriorates.
Moreover, if the diameter of the trench is smaller and smaller, the thickness of the arsenic doped glass film which is the source of the solid phase diffusion cannot be ensured in a sufficient way. As a result, it is difficult to form an impurity diffused layer of high impurity concentration on the surface of the trench.
If the arsenic doped glass film is deposited deep enough to embed the trench therewith to ensure the above-stated film thickness of the arsenic doped glass film, the impurity diffused layer of high impurity concentration is not necessarily formed. If formed, this causes the problem that it is difficult to peel off the arsenic doped glass in the later step.
If the diameter of the trench is smaller, the following problems also occur. Namely, when an arsenic doped amorphous silicon film is embedded into the trench, voids occur which cause problems in later manufacturing steps.
Specifically, provide that a plurality of trench capacitors are formed and elements are isolated in a region including the two trenches by Shallow Trench Isolation (to be described later and referred to as STI hereinafter). In this case, the arsenic doped amorphous silicon film present in the above-stated region is etched away and thermal oxidation is conducted onto the entire portion. During the etching process, voids occur within the arsenic doped amorphous silicon film and the portions of the arsenic doped amorphous silicon film where the voids appear are oxidized to thereby generate defects.
In the manufacturing process of semiconductor chips having trench structure, the number of steps is increasing to ensure necessary capacity. The increased number of steps needs to be reduced by adopting effective process.
Meanwhile, element isolation is conducted by using one of the local oxidation methods, i.e., LOCOS element isolation. According to the LOCOS element isolation,, the oxide film bites into the element formation region, which phenomenon is called bird's beak, and the effective area of the element formation region decreases. For that reason, the LOCOS element isolation is not effective for high integration purposes.
In view of the above, the STI has been widely used in recent years. The STI is the method by which a shallow groove serving as an element separation trench is formed on the surface of the substrate and the shallow trench is filled with the element isolation insulating film. Unlike the LOCOS element isolation, the STI does not cause a bird's beak. Due to this, a decrease in the area of the element formation region is prevented, which is therefore suitable for high integration purposes.
The conventional STI has, however, the following problems. The trench of this type is formed by RIE, and uneven portions are generated on the inner surface of the trench.
As a result, the phenomenon that part of the channel of the MOS transistor cell is turned on earlier than the rest and that transistor characteristics thereby deteriorate. In addition, since it becomes difficult to embed a favorable shaped element isolation insulating film into the trench, defective element isolation occurs and reliability deteriorates.